The present embodiments relate to memory configurations. In one group of the present embodiments, they relate to microprocessors, and are more particularly directed to microprocessors having circuits, systems, and methods for re-mapping memory row redundancy by converting an original address to a spare row address during a two cycle cache access. In another group of the present embodiments, they relate to circuits, systems, and methods for remapping memory column redundancy.
In the digital memory art, it is known that after a memory is constructed there is some statistical probability that one or more rows of the memory may be found to be defective. In other words, although a row was constructed to store a certain predetermined number of bits of information, after construction it is determined through testing that the row, for whatever reason, is inoperable and thus cannot store the information as originally intended. Given this probability, often a memory includes one or more so-called redundant or spare rows, and information which originally would have been stored to, and read from, the defective row is somehow instead stored to, and read from, one of the spare rows.
Given the spare row redundancy described above, in one prior art approach each of those rows in the memory also includes a row enabling fuse which determines whether the corresponding row may be energized. Moreover, each spare row includes a group of decoder fuses to decode the address to energized the corresponding row. Thus, if a row is found to be defective, the row enabling fuse is configured (e.g., disabled) so that the defective row cannot be energized. Further, the decoder fuses for one of the spare rows are then configured so that the decoder decodes an incoming address intended for the defective row and instead addresses the spare row. While this approach is heavily used, it has various drawbacks. For example, fuse construction may add complexity to the construction process. As another example, fuses also require additional usage of area on the integrated circuit. Given these considerations, note further the number of fuses required for the prior art described above. Specifically, the total number of fuses required equals the number of rows plus the number of spare rows times the sum of the number of bits to decode an address for the memory plus one enable bit for each spare row. For example, for a 256 line memory with two independent spare rows, a total of 274 fuses are required (256 row enabling fuses plus 2* (8 decode fuses+1 enable fuse)). Moreover, note that the great majority of these fuses are not located in one place, but are placed along each row. These as well as other drawbacks will be appreciated by a person skilled in the art.
Given the above observations about row implementation in the digital memory art, it is likewise known with respect to memory columns that after a memory is constructed there is some statistical probability that one or more columns of the memory may be found to be defective. Thus, although a column was constructed to be able to either output, input, or both input or output a bit of information, after construction it is determined through testing that the column, for whatever reason, is inoperable and thus cannot communicate the information as originally intended. Given this probability, often a memory includes one or more so-called redundant or spare columns, and information which originally would have been stored to, and read from, the defective column is somehow instead stored to, and read from, one of the spare columns.
Given the spare column redundancy described above, in one prior art approach detailed later each of those columns is directed through one or more multiplexers to an external column, and those multiplexers are controlled by fuses fixed between successive control inputs to the multiplexers. Thus, if a column is found to be defective, a fuse controlling the multiplexer through which the defective column would otherwise communicate is configured (e.g., disabled) so that the defective column cannot either receive information in the case of input, or produce information in the case of output. While this approach may be used, it too has various drawbacks. For example, in some configurations, if more than one column is identified as defective then this prior art approach by itself is insufficient since it is capable of only excluding one column from reaching the external connections of the memory configuration. As another example, the number of fuses required by this prior art approach is one greater than the number of output columns and, thus, for a large memory, there is correspondingly a large number of fuses required. As another example, note the fuses are typically physically oriented between output columns of the memory configuration and, therefore, require considerable space relative to the columns of the memory configuration
In view of the above, there arises a need to address various drawbacks of the prior art, and improve upon prior art approaches as is accomplished by the inventive embodiments discussed below.